最終更新日時： 2021/06/08 16:14:33
New circuit design environment with UML and NSL.
Overtone provides new hardware design platform for model base using “UML to RTL” technique. With this new technique “UML to RTL”, it improves the productivity of engineers and also to realize the competitive advantage to enhance the critical architecture design capabilities in upstream process of product development.
NSL (Next Synthesis Language) is new hardware description language (HDL) for semiconductor device development. NSL has distinctive feature that is able to describe a processing subject. But Verilog-HDL and VHDL describes with a register subject. In addition, there are the following features. -NSL is controllable language by the design engineer, because NSL is able to describe behavior level. So it is easy to realize the design idea. -NSL is high productivity language with Object-oriented design. -Able to convert easily from C/C++ model, because NSL has a simple and familiar syntax. -Able to coexist with the current design property such as IP core by RTL(Verilog-HDL/VHDL). -NSL has high affinity for UML. -Able to generate secure synthesizable RTL format include SystemC. Therefore NSL is easy to learn. Do not become concerned about learning new hardware description language. Please try and just use it!
Value of “UML to RTL” method
Reduction of a man-hour of development（Front-end Design efficiency is 50% UP） -NSL source code which is described compendiously due to structure and syntax of NSL, has good readability. (1/4 times smaller than Verilog-HDL code) -Able to information sharing and smooth communication in the development group member by means of UML diagrams. (Reduction of the wasted time for the meeting and the making of document) Eliminating the distinction between the engineers (skill gap) -Homogenizing of outputted RTL code file. In fact, a beginners’ class engineer can realize the optimal circuit (speed performance and scale) which is the same as an expert level. A low-cost environment development (max 50% cost cut) -It is not necessary to design and to manage individually of RTL model (Verilog HDL/VHDL/SytemC). Able to consolidate design property such as IP core by means of NSL model. -Able to create handily the hardware software Co-verification environment by outputted SystemC model.
In case of Design House, Reduction in their man-hour cost of design that is enhance their business competitiveness. In case of IP Provider, Reduction in development / maintenance cost for IP Core. (50% cost cut) In case of Manufacturer/Service Provider, Enhance the design efficiency of upper process, such as architecture and algorithm design, so enhance their business competitiveness. (Reduction in their waste meetings and documents)